Professional Background:

Tokyo Electron Limited (TEL) September 2001- 2007

Applied Materials Japan, Inc (AMJ)  January 1998 - August 2001

Mitsubishi Electric Corp. (Melco) April 1978 - January 1998                                                                                                       

Education:

Ph.D., Electric & Electronics Engineering, Sophia University, Tokyo Japan 

Master of Electric & Electronics Engineering, Sophia University, Tokyo Japan 

Bachelor of Technology, Electric and Electronics Engineering, Sophia University,

Tokyo Japan

Post Doctoral Research, Sophia University, Tokyo Japan  

Responsibilities:

As Assistant Vice President and Director of Asian and Pacific Rim Strategic Alliances, Dr. Hirayama will be responsible for the development and implementation of a world-class, externally funded program involving research and development, business and educational initiatives that utilize the advanced fine patterning and extensive materials characterization capabilities at CNSE. The program is designed to support the growth of further collaborative activities with industry and academia around the world, and to attract additional global corporate partners, with an emphasis on Asian corporations such as Nikon, Hitachi, Revera, Wafermasters, Matheson Tri Gas and Seiko Instruments.

Research Description:

Small geometry silicon transistors are required to fabricate high density memory devices and high-end logic devices for high speed operation and low power consumption. The channel length is less than 20 nm and the gate dielectric thickness in transistors is less than 1 nm of an equivalent thickness of silicon dioxide. These sizes are rapidly approaching the order of the silicon crystal lattice. Although the semiconductor industry has succeeded in fabricating high performance devices with nanometer scale dimensions, fabricating reliable, high yield 32 nm and beyond devices has proven to be very difficult. For advanced device applications, high speed operation can be achieved by the modulation of the silicon crystalline structure by introducing Ge to form Si1-xGex alloy. Si-Ge substrates exhibit higher electron mobility and enable the fabrication of transistors with novel three dimensional structures. Theoretical analysis and validation of physical and manufacturability limits are required to integrate new materials into nanometer scale integrated circuits. This is the motivation for Dr. Hirayama's research work in the areas of fundamental characterization and analysis of new materials and the integration and understanding of silicon transistors at nanometer scale dimensions.

There are three approaches to elucidate the mechanism of transistor action.

1) Simulation of transistor action at the atomic scale in order to develop fundamental understanding of band theory and recommend corrective actions in nanometer scale device fabrication.

2) The theoretical consideration of the transistor behavior of nanometer scale devices from the crystallography, quantum physics and material science point of view.

3) The experimental characterization of actual nanometer scale transistor devices. To perform these measurements, Dr. Hirayama will utilize the advanced fine patterning capability and the extensive materials characterization capability at CNSE to understand bulk, surface, interface and patterned structures. His ideas are to use micro Raman spectroscopy and XPS for detailed microscopic characterization of materials and devices. Dr. Hirayama will closely work with other CNSE faculty in order to engage in an active exchange of information to stimulate and enhance research activities. This work requires large scale science and engineering.  It requires a global collaboration with academic and industrial entities with specialized materials processing and characterization capabilities. Dr. Hirayama will work mainly in experimental activities at CNSE on transistor characterization and surface analysis for future device nodes and detailed materials characterization using very high resolution, multi wavelength micro Raman spectroscopy, but he also will coordinate collaborative activities with global laboratories.

To achieve this research plan, Dr. Hirayama plans to attempt to enhance the CNSE research environment by attracting additional global partners to form effective consortia. For leading edge lithography and measurement, he will work with Nikon and Hitachi High Tech, respectively. Dr. Hirayama also will coordinate XPS work with Revera and very high resolution, multi wavelength micro Raman spectroscopy with Wafermasters. Matheson Tri-Gas will be an excellent materials supplier and Seiko Instrument will be an excellent functional device supplier. These goals can only be met at CNSE to leverage the simulation, fabrication and analytical capabilities of CNSE with the outstanding network of partners working at the facility.

Awards:

Solid State Devices and Materials Award, 2004 "Fabrication of Storage Capacitance-Enhanced Capacitance-Enhanced Capacitors with a Rough Electrode" with Y. Hayashide, H. Miyatake, J. Mitsuhashi, T. Higaki and H. Abe.

Publications:

"Electron Beam Direct Writing Techniques for the Development of Sub-Quarter-Micron Devices" T. Fujino, H. Maeda, Y. Kimura, H. Horibe, Y. Imanaga, H. Shinkawata, S. Nakao, T. Kato, Y. Matsui, M. Hirayama, H. Abe and A. Yasuoka (Jpn. J. Appl. Phys. Vol 35 (1996)

"Electron Traps and Excess Current Induced by Hot-Hole Injection into Thin SiO2 Films" K. Kobayashi, A. Teramoto, Y. Matsui, M. Hirayama and A. Yasuoka (J. Electrochemical Society Vol 143 (1996)

"Ultra Silicon Nitride Films Fabricated by Single-Wafer Processing Using an SiH2Cl2-NH3-H2 System and In Situ H2 Cleaning" K. Kobayashi, Y. Inaba, T. Ogata, T. Katayama, H. Watanabe, Y. Matsui and M. Hirayama (J. Electrochemical Society Vol. 143 (1996)

"An Advanced Plannarizing Interlayer Dielectric Using SiH4 and H2O2 Chemistry" M. Matsuura and M. Hirayama (Dry Process Symposium 1995)

"Electron Trap and Excess Current Induces by Hot-Hole Injection into Thin SiO2 Films" K. Kobayashi, A. Teramoto and M. Hirayama  (The 33rd Annual International Reliability Physics Symposium, (1995)

"Charge Transport in Ultra thin Silicon Nitride" K. Kobayashi, A. Teramoto and M. Hirayama (J. Electrochemical Society Vol. 142 (1995)

"Model for the substrate hole current based on thermionic hole emission from the anode during Fowler-Nordheim electron tunneling in n-channel metal-oxide-semiconductor field effect transistors" K. Kobayashi, A. Teramoto and M. Hirayama (K. Kobayashi, A. Teramoto, M. Hirayama and Y. Fujita (J. Applied Physics Vol 77 (1995)

"Dielectric Breakdown and Current Conduction of Oxide/Nitride/Oxide Multi-Layer Structures", K. Kobayashi, H. Miyatake, M. Hirayama, T. Higaki and H. Abe (J. Electrochemical Society, Vol. 139 (1992)

"Local-Oxidation-Induced stress Measured by Raman Microprobe Spectroscopy" K. Kobayashi, Y. Inoue, T. Nishimura, M. Hirayama, Y. Akasaka and T. Kato (J. Electrochemical Society, Vol. 137 (1990)

"Fabrication of Storage Capacitance-Enhanced Capacitors with a Rough Electrode" Y. Hayashide, H. Miyatake, J. Mitsuhashi, M. Hirayama, T. Higaki and H. Abe (Jpn. J. Appl. Phys. Vol. 29 (1990)

"Optical Absorption in Silicon Oxide Film Near the SiO2/Si Interface" T. Haga, N. Miyata, K. Moriki, M. Fujisawa, T. Kaneoka, M. Hirayama, T. T. Matsukawa and T. Hattori (Jpn. J. Appl. Phys. Vol 29 (1990)

"Growth Mechanism of Silicon Plasma Anodic Nitridation" M. Hirayama, T. Matsukawa, H. Arima, Y. Ohno and H. Nakata (J. Electrochemical Society Vol.132 (1985)

"Plasma Anodic Nitridation of Silicon in N2-H2 System" M. Hirayama, T. Matsukawa, H. Arima, Y. Ohno, N. Tsubouchi and H. Nakata (J. Electrochemical Society Vol. 131 (1984))

"A Highly Reliable N-MOS Process for One megabit Dynamic Random Access Memory"  T. Matsukawa, M. Inuishi, J. Mitsuhashi, M. Hirayama, K. Tsukamoto, S. Uoya,  T. Yoshihara and H. Nakata ( IEEE International Electron Devices Meeting, (1984)

"High-Pressure Oxidation for Thin Gate Insulator Process" M. Hirayama, H. Miyoshi, N. Tsubouchi and H. Abe (IEEE Trans. Electron Devices Vol ED-29 (1982)

"Time Dependent dielectric Breakdown of Thin SiO2 Films" M. Hirayama, S. Asai, H. Matsumoto, K. Sawada and K. Nagasawa (Jpn. J. Appl. Phys. Vol. 20 (1981)

"Effect of Long-Term Stress on IGFET Degradations Due to Hot Electron Trapping" H. Matsumoto, K. Sawada, S. Asai, M. Hirayama and K. Nagasawa (IEEE Trans. Electron Devices Vol. ED-28 (1981)