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Recognized academic and technical experts in nanoelectronics from CNSE were selected to deliver presentations at SEMICON West 2009, a leading industry conference and trade show is being held July 14 through 16 in San Francisco, CA.
Dr. Robert Geer, CNSE Vice President for Academic Affairs and Chief Academic Officer, and Professor of Nanoscale Science, and Richard Brilla, CNSE Vice President for Strategy, Alliances and Consortia, were scheduled to speak as part of SEMICON's Device Scaling TechXPOT, which is being held in Moscone Center's North Hall.
Geer's presentation, entitled "Evolution of On-Chip Interconnects for Equivalent Scaling: To 22nm and Beyond," was given on Tuesday, July 14. Geer described how the transition to multi-core on-chip architectures has rapidly changed the landscape for end-of-roadmap interconnect paradigms, highlighting the need to leverage 3D processing, novel signaling approaches, new material introduction and post-CMOS switch integration to maintain equivalent scaling well beyond 22nm.
Brilla discussed "Accelerated Development - Extending Moore's Law" on Wednesday, July 15 at 11:50 a.m., in which he outlined how the unique CNSE paradigm allows integration of tools, materials and resources, and results in accelerated and cost-effective process development. In particular, he focused on the collaborations between CNSE and several of its global corporate partners, including International SEMATECH and Atotech.
One of the largest industry conferences and trade shows, SEMICON West annually attracts more than 45,000 attendees from over 15 countries, as well as the world's leading nanoelectronics technology companies, which are responsible for every major technology breakthrough since the birth of the integrated circuit.
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