About Us > Faculty & Staff > Technical Staff > Tricia E. Burroughs Chemical & Mechanical Planarization Process Engineering

Professional Background:

• CMP Process Engineering - College of Nanoscale Science and Engineering, University at Albany
• Lead Process Engineer, CMP - Applied Materials, Qimonda/Global Foundries Account, Richmond, VA and Dresden, Germany. 2007 - 2009
• Senior Process Engineer, CD-SEM, SEM, and CMP - Applied Materials, Qimonda Account, Richmond, VA. 2004 - 2007
• Key Account Technologist, CMP - Applied Materials, Intel, Santa Clara, CA. 2003 - 2004
• Key Account Technologist, CMP - Applied Materials, Europe and North America, Santa Clara, CA. 2002 - 2003
• 300mm R&D Process Engineer, CMP - Applied Materials, Santa Clara, CA. 2000 - 2002
• EH&S Engineer - HMT Disk Drive Technology, Fremont, CA. 1999 - 2000
• EH&S Engineer - Raychem, Menlo Park, CA. 1997 - 1999

Responsibilities:

As CNSE Chemical and Mechanical Planarization (CMP) process owner, Ms. Burroughs is responsible for the development and sustainability of all CMP process steps in CNSE's, and their partners, device flows. These include STI, Poly, ILD Oxide, and Copper CMP. Her responsibility extends to the maintenance and improvement of the group's STI and Full Replacement Gate modules.

Tricia is currently working to develop the CMP steps enabling Interconnect and ReRAM integrations. Her faculty development projects included providing planarization for grapheme and carbon nanotube devices.

Relevant Publications and Presentations:

• "Use of Serpentine-Comb Resistors to Develop and Monitor the Interconnect CMP Processes that Enable High-K Metal Gate-Last CMOS" exp ICPT 2010
• "iAPC vs. Lot to Lot Control and Open Loop for CMP" Applied Materials ET Conference 2008
• "Reflexion LK - New Monitoring Methods for Tool Qualification and Consumable Extendibility for Optimum Tool Productivity" Applied Materials ET Conference 2006
• "Challenges and Methodologies of Fab to Fab CD-SEM Matching" IEEE/SEMI ASMC 2006
• "Impact of DIW Sensors on Silicon and SOI CMP and the Development of Edge Contact Wafer Exchanger Stations" Applied Materials ET Conference 2004
• "Prime Silicon and Silicon-on-Insulator (SOI) CMP Opportunities and Challenges" Applied Materials ET Conference 2002
• Si and SOI CMP Processing. One week course developed and taught to SOITEC in Bernin, France.

Invention Alerts:

• Groove Design for Si and SOI Haze Reduction - Applied Materials
• Mathematical Methodologies for APC Control of Multi-Zone CMP Heads - Applied Materials
• Top Lead Area-Reduction Design Rule to Improve Wafer Die Yield - CNSE
• Serpentine-Comb Design to Monitor Interconnect Level CMP - CNSE
• 45 Degree Notching of Small Silicon Features Using CMP - CNSE
• Copper Final Polish for Chemical Copper-Copper Bonding - CNSE