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Mohamad Jahanbani

Mohamad Jahanbani
Jahanbani, Mohamad Wet Clean / Surface Preparation Process Engineer

Professional background:

  • Motorola/Freescale Semiconductor, 1995-2008. Wet cleans Senior Process Development Engineer
  • FEOL Surface preparation Engineer, Sematech Corp. 1993-1995
  • Hot Process/CVD/Wet cleans Engineer, IBM Corp. 1987-1993.

Degrees:

  • M.S. Electrical Engineering, Howard University, Washington D.C., 1987
  • B. S. Electrical Engineering, University of District of Columbia, Washington D.C., 1983

Job Description:

  • Senior process development engineer for advanced cleans development for High-K/metal gate for 32 nm and beyond.
  • Provide CNSE technology development consortia partners wet clean solutions that meet their requirements.
  • Contribute to definition and development of CNSE's FEOL process flows for advanced technologies

Accomplishments:

  • Leader for wet cleans of multiple international and domestic wafer fab start up teams
  • Member of Motorola-Siemens (Infineon) first 300mm start up in Dresden Germany as well as 5 other joint ventures/Alliance technology developments.
  • Member of Advanced Products Research Development Laboratory technology development team for Motorola/Freescale working on for Advanced logic CMOS/32nm, memory, NVM, SMOS, Quantum dots, BiCMOS among others.
  • Member of Motorola/Freescale technical advisory committee for wets tool selection as well as technical ladder.

Issued Patents:

1- Process of forming an electronic device including a layer formed using an inductively coupled plasma, #: 7491622

2- Device for performing surface treatment on semiconductor wafers, #6564469

3- Method of forming an electronic device, #7214590

4- Method for elimination of excessive field oxide recess for thin Si SOI, #7037857

5- Method of Forming Trench Isolation In a Semiconductor Device, #PCT/US2006/008253

6- Removing Metal Using an Oxidizing Chemistry, #11426755

Publications:

Author and co-author for 56 publications. Recent publications:

  • Low-resistance PMOS contacts for the 45nm node. Stefan Zollner, Paul Grudowski, Dharmesh Jawarani, Mike L. Kottke, Rich B. Gregory, Xiang-Dong Wang, David Theodore, W. J. Taylor, Bich-Yen Nguyen, Cristiano Capasso, Mark Raymond, Dean Denning, Kyuhwan Chang, Ross Noble, M. Jahanbani, Scott Bolton, Phil Crabtree, Darren Goedeke, Marc Rossow, Murshed Chowdhury, Heather Desjardins, Aaron Thean. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA MRS 2007 spring meeting, San Francisco, CA, April 9-13, 2007.
  • Assessment of CMOS Performance Via Global and Local Condensation, V. Vartanian, A. Thean, T. White, B-Y. Nguyen, S. Zollner, M. Canonico, M. Kottke, D. Theodore, H. Desjardins, L. Prabhu, R. Garcia, G. Spencer, V. Dhandapani, S. Murphy, J. Conner, P. Fejes, R. Rai, C. Parker, J. Hildreth, R. Noble, M. Jahanbani, J. Mogab, and S. Venkatesan, APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA. ICMI Banff, Alberta, Canada, 2006.
  • Evolution of near-noble metals on Si after thermal annealing observed with x-ray metrology. Stefan Zollner, Dharmesh Jawarani, Scott Bolton, Kyuhwan Chang, Ross Noble, Mo Jahanbani, Mark Raymond, Marc Rossow, Rich Gregory, John Alvis, Debby Eades, Gauri Karve, and Jon Cheek. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA. 53rd AVS International Symposium, San Francisco, 12-17 November 2006.
  • Improved Short Channel Device Characteristics with Stress Relieved Pre-Oxide (SRPO) And a Novel Tantalum Carbon Alloy Metal Gate/HfO2 Stack. H.-H. Tseng, C. C. Capasso, J. K. Schaeffer, E. A. Hebert, P.J. Tobin, D. C. Gilmer, D. Triyoso, M. E. Ramon, S. Kalpat, E. Luckowski, W. J. Taylor, Y. Jeon, O. Adetutu, R. Hegde, R. Noble, M. Jahanbani, B. E. White. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA. IEDM 2004.
  • Uniaxial Strain Enhancement in SOI Technology for the Improvement of Channel and Exterior Resistance. Da Zhanga), D. Goedeke, V. Dhandapani, J. Hildreth, C.C. Fu, T. Kropewnicki, A. Lu, M. Jahanbani, H. Martinez, R. Noble, D. Eades, N. Liu, L. Kang, B.Y. Nguyen, V. Kolagunta, M. Hall, J. Cheek, S. Venkatesan. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA. ECS, 2007.
  • Improved Short Channel Device Characteristics with Stress Relieved Pre-Oxide (SRPO) for TaSiN /HfO2 Gate Stack. H.-H. Tseng, P. J. Tobin, M. E. Ramón, S. Kalpat, J. K. Schaeffer, E. A. Hebert, D. C. Gilmer, C. C. Capasso, R. Noble, M. Jahanbani, S. Semavedam. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA.
  • Uniaxial and Biaxial Strain for CMOS Performance Enhancement , B-Y Nguyen, D. Zhang, A. Thean, P. Grudowski, V. Vartanian, T. White, S. Zollner, D. Theodore, B. Goolsby, H. Desjardins, L. Prabhu, R. Garcia, J. Hackenberg, V. Dhandapani, S. Murphy, R. Rai, J. Conner, P. Montgomery, C. Parker, J. Hildreth, R. Noble, M. Jahanbani, D. Eades, J. Cheek, B. White, J. Mogab, S. Venkatesan. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA. ISTDM 2006.
  • Platinum Silicide Contacts for PMOS Transistors. D. Denning[1], S. Zollner, S. Bolton, M. Rossow, M. Jahanbani, K. Chang, D. Goedeke, P. Grudowski, R. Noble, D. Jawarani, R. Gregory, M. Kottke. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA.
  • Metrology of Silicide Contacts for Future CMOS. Stefan Zollner, Rich Gregory, Mike Kottke, Victor Vartanian, Xiang-Dong Wang, Michael Canonico, David Theodore, Peter Fejes, Mark Raymond, Xiaoyan Zhu, Dean Denning, Scott Bolton, Kyuhwan Chang, Ross Noble, Mo Jahanbani, Marc Rossow, Darren Goedeke, Stan Filipiak, Ricardo Garcia, Dharmesh Jawarani, Bill Taylor, Bich-Yen Nguyen, Phil Crabtree, Aaron Thean. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA 2007 Int. Conference on Frontiers of Characterization and Metrology for Nanoelectronics Gaithersburg, MD, March 28, 2007.
  • Source/Drain Stressor Device Development on SOI Sustrate. Da Zhang, B.Y. Nguyen, B. Goolsby, J. Hackenberg,V. Dhandapani, J. Hildreth, R. Noble, M. Jahanbani, S. Filipiak, T. White, M. Mendicino, A. Haggag, M.Zavala, P. Montgomery, D. Theodore, S. Murphy, R.Rai, J. Jiang, K. Kim, D. Sieloff, N. Cave, V. Kolagunta, J. Cheek, S. Venkatesan, J. Mogab. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA MRS Symposium, 2006.
  • Evolution of near-noble metals on Si after thermal annealing observed with x-ray metrology. Kyuhwan Chang, Stefan Zollner, Dharmesh Jawarani, Scott Bolton, Ross Noble, Mo Jahanbani, Mark Raymond, Dean Denning, Marc Rossow, Rich Gregory, Q. Xie, John Alvis, Debby Eades, Gauri Karve, and Jon Cheek. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA Silicide Workshop. Ghent, Belgium, September 22, 2006.
  • Evolution of Ni on Si after thermal annealing observed with x-ray reflectivity. Stefan Zollner, Dharmesh Jawarani, Scott Bolton, Kyuhwan Chang, Ross Noble, Mo Jahanbani, and Marc Rossow. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA Texas Section Meeting of the American Physical Society Arlington, TX, October XX, 2006.
  • Dual silicide CMOS integration with low-resistance PtSi PMOS contacts. Stefan Zollner, Paul Grudowski, Aaron Thean, Dharmesh Jawarani, Gauri Karve, Ted White, Scott Bolton, Heather Desjardins, Murshed Chowdhury, Kyuhwan Chang, Mo Jahanbani, Ross Noble, Luke Lovejoy, Marc Rossow, Dean Denning, Darren Goedeke, Stan Filipiak, Ricardo Garcia, Mark Raymond, Veer Dhandapani, Da Zhang, Laegu Kang, Phil Crabtree, Xiaoyan Zhu, Mike L. Kottke, Rich Gregory, Peter Fejes, X.-D. Wang, David Theodore, W.J. Taylor, Bich-Yen Nguyen, APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA IEDM 2006.
  • Strain Engineering for Performance Scaling. T. White, V. Vartanian, B-Y. Nguyen, D. Zhang, A. Thean, P. Grudowski, S. Zollner, D. Theodore, B. Goolsby, H. Desjardins, L. Prabhu, R. Garcia, D. Tekleab, J. Hackenberg, V. Dhandapani, M. Canonico, V. Adams, S. Murphy, R. Rai, J. Conner, P. Montgomery, C. Parker, J. Hildreth, R. Noble, M. Jahanbani, D. Eades, J. Cheek, B. White, J. Mogab, and S. Venkatesan. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA Semicon West 10-13 July, 2006.
  • Low-resistance PtSi PMOS contacts with 65nm dual silicide CMOS integration. Stefan Zollner, Paul Grudowski, Gauri Karve, Ted White, Aaron Thean, Dharmesh Jawarani, Scott Bolton, Heather Desjardins, Murshed Chowdhury, Kyuhwan Chang, Mo Jahanbani, Ross Noble, Luke Lovejoy, Marc Rossow, Dean Denning, Darren Goedeke, Stan Filipiak, Ricardo Garcia, Mark Raymond, Veer Dhandapani, Da Zhang, Laegu Kang, Phil Crabtree, Xiaoyan Zhu, Mike L. Kottke, Rich Gregory, Peter Fejes, X.-D. Wang, David Theodore, W.J. Taylor, Bich-Yen Nguyen. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA VSLI 2007.
  • Characteristic Study of SOI eSiGe Technology. D. Zhang, L. Kang, D. Goedeke, A. Nagy, V. Dhandapani, J. Hildreth, C.C. Fu, T. Kropewnicki, M. Jahanbani, H. Martinez, R. Noble, D. Eades, B.Y. Nguyen, V. Kolagunta, M. Hall, J. Cheek, S. Venkatesan, APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA SOI 2007.
  • Metrology Of Silicide Contacts For Future CMOS. Stefan Zollner, Richard B. Gregory, M.L. Kottke, Victor Vartanian, Xiang-Dong Wang, David Theodore, P.L. Fejes, J.R. Conner, Mark Raymond, Xiaoyan Zhu, Dean Denning, Scott Bolton, Kyuhwan Chang, Ross Noble, Mohamad Jahanbani, Marc Rossow, Darren Goedeke, Stan Filipiak, Ricardo Garcia, Dharmesh Jawarani, Bill Taylor, Bich-Yen Nguyen, P.E. Crabtree, and Aaron Thean. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA.
  • Etch and Epitaxy Process Development in Device Integration D. Zhang, B.-Y. Nguyen, M. Jahanbani, R. Noble, B. Goolsby, X.D. Wang, B. Xie, ECS ISTC, 2004.
  • Embedded SiC S/D NMOS on Thin Body SOI Substrate with Drive Current Enhancement D. Zhang, B.Y. Nguyen, S. Zollner, T. White, V. Vartanian, B. Goolsby, V. Dhandapani, R. Garcia, J. Cooper, D. Sing, V. Adams, D. Theodore, M. Canonico, S. Murphy, J. Conner, J. Jiang, M. Jahanbani, R. Noble, P. Montgomery, M. Bauer, P. Tomasini., C. Arena, C. Werkhoven, H. Kirby, V. Kolagunta, J. Cheek, B.E. White, J. Mogab, S. Venkatesan, APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA VLSI 2006.
  • Undoped channel PMOS Fin FET with deposited Titanium Nitride Gate Electrode over SiO2 Gate dielectric for low leakage applications. L. Mathew, S. Kalpat, T. Stephens, R. Noble, M. Jahanbani, B. Goolsby, R. Mora, M. Sadd, R. Rai, S. Becker, C. Parker, V. P. Tridedi, D. Sing. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA VLSI 2006.
  • 1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations. Paul Grudowski, Vance Adams, Xiang-Zheng Bo, Konstantin Loiko, Stan Filipiak, John Hackenberg, Mo Jahanbani, Marijean Azrak, Sinan Goktepeli, Mehul Shroff, Wen-Jya Liang, SJ Lian, Venkat Kolagunta, Nigel Cave, Chi-Hsi Wu, Mark Foisy, HC Tuan, and Jon Cheek. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA VLSI 2006.
  • Recessed S/D SiGe on Thin Body SOI Substrate Providing PMOS Drive Current Enhancement. D. Zhang, B.Y. Nguyen, T. White, B. Goolsby, T. Nguyen, V. Dhandapani, J. Hildreth, M. Foisy, V. Adams, Y. Shiho, A. Thean, D. Theodore, M. Canonico, S. Zollner, S. Bagchi, S. Murphy, R. Rai, J. Jiang, M. Jahanbani, R. Noble, M. Zavala, R. Cotton, D. Eades, S. Parsons, P. Montgomery, A. Martinez, B. Winstead, M. Mendicino, J. Cheek, J. Liu, P. Grudowski, N. Ranami, P. Tomasini., C. Arena*, C. Werkhoven*, H. Kirby*, C.H. Chang. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA. VLSI 2005.
  • Properties of nickel silicide formed by rapid thermal processing of thin Ni layers on Si (001). Stefan Zollner, Scott Bolton, Dharmesh Jawarani, Xiaoyan Zhu, Michael Canonico, Richard B. Gregory, Qianghua Xie, Peter L. Fejes, Michael Kottke, John Alvis, Ross Noble, Colita Parker, Mo Jahanbani, Bich-Yen Nguyen, Jon Cheek. Freescale Semiconductor, Inc Austin, TX 78721. Chiang-Ming Chuang, Tan-Chen Lee. Taiwan Semiconductor Manufacturing Company Austin, TX 78721.
  • Thin-Film Metrology for Nickel Silicide Process Control. Stefan Zollner, Scott Bolton, Marc Rossow, Kyuhwan Chang, Ross Noble, Mohamad Jahanbani, Dharmesh Jawarani, Xiaoyan Zhu, Victor Vartanian, Mark Raymond, Mike Kottke, Richard B. Gregory, and John Alvis. Freescale Semiconductor, Inc., Austin Technology and Manufacturing Center, MD K10, 3501 Ed Bluestein Blvd, Austin, TX 78721. ICMI 2006.
  • Process and integration for strained Device Development. Da Zhang, Bich-Yen Nguyen, Mo Jahanbani, Ross Noble, Brian Goolsby, Xiangdong Wang, Qianghua Xie. Freescale Semiconductor, Inc. 3501 Ed Bluestein Blvd Austin, TX 78721. ECS-ISTC 2004, Shanghai China, September 2004.
  • Defect Passivation with Fluorine in a TaxCy/High-K Gate Stack for Enhanced Device Threshold Voltage Stability and Performance. H.-H. Tseng, P.J. Tobin, E. A. Hebert, S. Kalpat, M. E. Ramón, L. Fonseca, Z. X. Jiang, J. K. Schaeffer, R. I. Hegde, D. Triyoso, S. J.  Rhee,  D. C. Gilmer, W. J. Taylor, C. C. Capasso, O. Adetutu, D. Sing, J. Conner, E. Luckowski, A. Haggag, S. Backer, R. Noble, M. Jahanbani, B. E. White. APRDL, Freescale Semiconductor Inc., Austin, TX 78721, USA.